This invention relates to a layout of an integrated high voltage Darlington pair and, more particularly, to a layout which reduces the large layout area of a conventional high voltage Darlington pair.
In order to comprehend this invention it is necessary to study the circuit and the layout of high voltage transistors.
Referring to FIG. 1, there is shown an example of a circuit diagram of a high voltage transistor Q. The emitter 10 is connected to a high voltage+V the collector 12 is grounded and the base 14 is connected to an input Vin. The input Vin has a voltage which is close to the voltage of the emitter 10.
In high voltage applications, the transistors are designed to withstand high voltages as high as 1000 volts by constructing a field plate between the base and the collector of each transistor. The field plate spaces out the field lines to avoid field concentrations. The field plate also acts as a resistance shown by R.
Referring to FIG. 2, there is shown a cross sectional view of the layout 20 of the transistor Q of FIG. 1 on a p-type substrate 22. The bipolar transistor comprises a n-type well or tub 24, a p+region 10 within the n-well 24 to function as the emitter 10 of the transistor Q. A n+region 14 within the n-well 24 provides a contact for the n-well 24. The n-well 24 functions as the base of the transistor Q and the n+region 14 is the contact of the base. A p+region 12 outside of the n-well 24 is the collector of the transistor Q. In order to have a high voltage transistor, the p+region 12 has to be separated from the n-well 24 (base) by a layer of field oxide 26 which accommodates an area for the field plate rings 28 and a field plate resistor 30. Under the field oxide, there is a layer of n--region 25 which is the drift region for the n-well 24. The n--region 25 increases the breakdown voltage of the transistor. The reason for having two n+regions 14, two p+regions 12 (collector) and two field oxide 26 regions is that the layout is circular.
Referring to FIG. 3 there is shown a top view of the layout of the high voltage transistor of FIGS. 1 and 2. Typically the transistors are made to be circular and therefore, the n-well 24 (base) and the emitter 10 will be located at the center and collector 12 will be a circular ring separated from the n-well 24 (base) by a large ring of field oxide 26 which accommodates an area for several field plate rings 28 and the field plate resistor 30. Field plate has to be overlaid on a layer of field oxide since the field plate has to sustain a large amount of voltage.
The field plate comprises a plurality of field plate rings 28 over a layer of field oxide 26 and a field plate resistor 30. It should be noted that under the field oxide 26, there is a layer of n--region 25. Each ring 28 of the field plate distributes an equal voltage around the field plate area. The field plate resistor 30 which is connected to all the rings 28 is also connected to the base and the collector by metal bonding 29 and 31 respectively. Due to a plurality of rings 28 required to distribute the high voltage difference between the base and the collector, the area that the rings of the field plate and the field oxide under the field plate occupy is quite large. Therefore, the layout of a high voltage transistor is very large.
For the purpose of simplicity hereinafter, the combination of field oxide ring 26, the layer of n--region 25 under the field oxide 26, the field plate resistor 30 and the field plate rings 28 will be referred to as "field plate".
Referring to FIG. 4, there is shown an example of a circuit diagram of a Darlington pair. It is well known in the art that a Darlington pair 40 is a circuit comprising two bipolar transistors Q1 and Q2 in which the base 42 of transistor Q2 is connected to the emitter 44 of transistor Q1. Also, the collectors 46 and 48 of both transistors Q1 and Q2 are connected to a common voltage V1. The base 50 of transistor Q1 is connected to the input Vin and the emitter 52 of the transistor Q2 is connected to a high voltage V.sub.2 which is more positive than V.sub.1.
Referring to FIG. 5, there is shown a top view of the layout of the high voltage Darlington pair 40 of FIG. 4. In the layout of a high voltage Darlington pair, two high voltage transistors Q1 and Q2 are constructed next to each other. However, since each transistor has a large ring 26 dedicated to the field plate, the two transistors used for a Darlington pair occupy a very large area.
Due to the high cost of the integrated devices, a high voltage Darlington pair with a large layout area becomes cost prohibitive. It is an object of this invention to reduce the layout area needed for a high voltage Darlington pair.